Multi-level ladder dac with dual-switch interconnect to ladder nodes

ABSTRACT

A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 14/823,820 (Docket TI-75236), filed Aug. 11, 2015, which claimed priority under USC §119(e) to U.S. Provisional Application 62/035,773 (Docket TI-75236P5), filed 11 Aug. 2014), which is incorporated by reference.

BACKGROUND

Technical Field

This Patent Disclosure relates generally to resistor ladder DACs (digital to analog converters), and more particularly to multi-level, multi-ladder DACs.

Related Art

Multi-level resistor ladder DACs can be used to provide extended voltage. The DAC can be configured with switch-interconnect first and second level resistor ladders, with the second-level ladder used to subdivide the voltage range present across a given resistor in the first-level ladder. For example, one possible configuration for a 12 bit DAC would consist of two ladders, with the first consisting of 64 resistors and the second, 63 resistors with 64 tap points. The resistance of all resistors, in both ladders, is the same. When placed in parallel with a given inner ladder resistor, the parallel resistance of the two ladders is 63/64 the resistance of an inner ladder resistor itself.

FIG. 1 illustrates a multi-ladder DAC with first and second level resistor ladders. The second-level ladder has taps (for example, 64) that feed into a high impedance buffer input (not shown). The second-level ladder top and bottom taps are switch-interconnected through transistor switches, with resistance (Rdson) value Rsw, respectively to the first-level ladder nodes just above and below a selected first-level ladder resistor N. The voltage at the top tap point is actually I×Rsw lower than the voltage at the node just above the selected first-ladder resistor N. The voltage at the bottom tap point is actually I×Rsw higher than the voltage at the node just below the selected first-ladder resistor N. This ladder switch-interconnect configuration results in an error at the transition between the top tap point for a selected first-ladder resistor N, and the bottom tap point of the first-level ladder resistor N−1 just above it equal to 2 IRsw. If the switch resistance is half of the ladder resistor resistance, the DNL (differential non-linearity) error is 1 LSB.

BRIEF SUMMARY

This Brief Summary is provided as a general introduction to the Disclosure provided by the Detailed Description and Drawings, summarizing aspects and features of the Disclosure. It is not a complete overview of the Disclosure, and should not be interpreted as identifying key elements or features of, or otherwise characterizing or delimiting the scope of, the disclosed invention.

The Disclosure describes apparatus and methods for a multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors.

According to aspects of the Disclosure, for each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

Other aspects and features of the invention claimed in this Patent Document will be apparent to those skilled in the art from the following Disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art multi-ladder DAC, including switch-interconnect between a first (inner) ladder, and a second (outer) ladder.

FIG. 2 illustrates an example embodiment of a multi-level ladder DAC with dual-switch interconnect to first-level ladder nodes, reducing DNL error from tap-point transitions between first-level ladder rungs (the transition between a top tap point of a ladder resistor N, and a bottom tap point of a ladder resistor N−1).

DETAILED DESCRIPTION

This Description and the Drawings constitute a Disclosure for the multi-level ladder DAC (multi-ladder) with a dual-switch interconnect to (first level) ladder nodes, including example embodiments that illustrate various technical features and advantages. The dual-switch ladder interconnect configuration reduces DNL at tap-point transitions between first-level ladder rungs.

In brief overview, a multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

FIG. 2 illustrates an example embodiment of a multi-level ladder DAC with dual-switch interconnect to first-level ladder nodes, reducing DNL error from tap-point transitions between first-level ladder rungs. That is, the transition between a top tap point of ladder resistor N, and a bottom tap point of a ladder resistor N−1.

A multi-level multi-ladder DAC includes first and second level resistor ladders, with switch interconnect between the resistor ladders. The switch-interconnect network include dual switches for each first-level ladder node. That is, for each first-level resistor [N], dual-switches connect to respective top and bottom nodes NT and NB.

That is, the switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRsw error, thereby improving DNL.

Specifically, for a selected first-level resistor N, the second level top and bottom tap points connect through separate switches to respective first-level nodes (outer loop). The second level resistor ladder connects at the top and bottom resistors through separate switches to respective first level nodes (inner loop). The inner loop includes all second-level tap points other than the top and bottom tap point (outer loop).

Because no current flows through the switches that tie the top and bottom tap points to the first-level ladder nodes, IRsw error is avoided. Specifically, DNL error is eliminated at the transition between first-level ladder rungs (N and N−1).

Advantages of a multi-level ladder DAC (multi-ladder) with a dual-switch interconnect to first-level ladder nodes include: (a) reducing DNL at transition points, (b) enabling use of lower resistances in the second ladder, which reduces RC delay, and increases sampling frequency, while maintaining good DNL at transition points.

The Disclosure provided by this Description and the Figures sets forth example embodiments and applications illustrating aspects and features of the invention, and does not limit the scope of the invention, which is defined by the claims. Known circuits, functions and operations are not described in detail to avoid obscuring the principles and features of the invention. These example embodiments and applications can be used by ordinarily skilled artisans as a basis for modifications, substitutions and alternatives to construct other embodiments, including adaptations for other applications. 

1. A DAC (digital to analog converter) circuit, comprising a first-first level resistor ladder including multiple series-connected resistors, including a resistor N connected to a previous resistor N−1 at a respective top ladder node NT, and to a next resistor N+1 at a respective bottom ladder node NB; a second-level resistor ladder including multiple series-connected resistors, starting with a top resistor RT and ending with a bottom resistor RB, and with tap nodes between each second-level resistor, each tap node connected to a tap switch operable to select the tap node as a respective tap point; and a switch-interconnect network configured to selectively connect the second-level ladder across each first-level resistor N at the NT and NB ladder nodes, including dual (first and second) interconnect switches selectively connectable to the NT ladder node; and dual (third and fourth) interconnect switches selectively connectable to the NB ladder node; such that, the first interconnect switch is operable to connect the NT node to a top tap switch operable to select the NT node as a top tap point, and the fourth interconnect switch is operable to connect the NB node to a bottom tap switch operable to select the NB node as a bottom tap point, the first and fourth switches are connected, forming an outer loop that includes the top tap point and the bottom tap point; and such that the second interconnect switch connects to RT, and the third interconnect switch connects to RB, forming an inner loop that includes the series-connected second-level resistors.
 2. The circuit of claim 1, wherein the top second-level resistor RT is sized such that the resistance value of RT plus the resistance of the second interconnect switch is equal to a target resistance; and the bottom second-level resistor RB is sized such that the resistance value of RB plus the resistance of the third interconnect switch is equal to a target resistance. 